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Hi Matt,
This depends on the implementation of the bus switch/arbitration controller.
The Wishbone SOC Bus spec does not describe how to write the interconnect,
it just provides the means to do so.

Richard

-----Original Message-----
From: cores-bounces@o... [mailto:cores-bounces@o...] On
Behalf Of Matt Ettus
Sent: Wednesday, April 25, 2007 2:55 AM
To: Discussion list about free open source IP cores
Subject: [oc] RMW and Wishbone

My question centers on the definitions of STB_O, CYC_O, and LOCK_O from 
the MASTER's perspective. 

In a previous discussion, it was said that the INTERCON can interrupt a 
MASTER's access to a SLAVE even when CYC_O was held high, thus the need 
for the LOCK_O signal to prevent that.  If that is true, then I would 
assert the following:

    In order to perform a true RMW cycle, LOCK_O is needed

However, in Appendix A.4.3, there is no mention of LOCK_O, and it 
implies that access to the SLAVE CANNOT be taken away as long as CYC_O 
is held asserted.

So, the question is -- without a LOCK_O signal, can a true RMW cycle be 
performed?

Matt

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