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Message
From: Paul Kahn<pkahn4oc@c...>
Date: Mon Apr 16 20:38:57 CEST 2007
Subject: [oc] DDR memory controllers
Hi all,
i'm looking for a ddr memory controller for use in a spartan3 and am not
sure
about the possible options, pros and cons. i found the following on the
opencores site:
* ddr_sdr ( http://www.opencores.org/projects.cgi/web/ddr_sdr/overview )
this one is ddr capable, but not marked as wishbone compatible. I'd like
to get more
input about it before choosing it, because i found quite a couple
forum/list messages where
people had problems with it. also, do any of you use it in a
wishbone-type configuration?
if so, did you design a wishbone bridge for it?
* mem_ctrl ( http://www.opencores.org/projects.cgi/web/mem_ctrl/overview )
this memory controller seems nice and wishbone-compliant, but i find no
mention
about DDR capability. it looks as if it could only use non-DDR sdram.
(correct me
if i'm wrong / if it does support DDR) ?
as for non-opencores sources, there's the xilinx memory interface
generator (mig007).
which i haven't tried so far (and the generated result is also not
wishbone compatible)
what about that? do you use that in a wishbone-type configuration? if
so, did you design
a wishbone bridge for it?
what other DDR controller solutions are there out there? (apart from
reinventing the
wheel and spend lots of time trying to design one myself, which i'd
really like to avoid)
what DDR controller do you use or recommend? what are the pros and cons?
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