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Message
From: Umair Siddiqui<umairsiddiqui84@g...>
Date: Mon Apr 16 13:08:14 CEST 2007
Subject: [oc] Verilog "Task" Help
/**** given code sample doesn't make sense but any ways ***/module Controller
(
input clk,
output reg wb_dat_o
);
always begin
wb_write(clk);
end
task wb_write;
input a;
begin
wb_dat_o = a;
end
endtask
/* OR */
always begin
wb_write;
end
task wb_write;
begin
wb_dat_o = clk;
end
endtask
endmodule
On 4/16/07, DigitalHomeSoutions@c... <DigitalHomeSoutions@c...> wrote:
> Help! I've tried everything I can think of to try and get the
> Verilog "Task" function to work with ISE but I keep getting errors that
> Xilinx is working on the issue or the service pack has the fix (didn't
> work).
>
> Can anyone tell me what the correct format is for using the "Task"
> function in ISE? Here is what I have so far:
>
> module Controller(
> input clk,
> output reg wb_dat_o);
>
>
>
> always begin
> wb_write(clk, wb_dat_o);
> end
>
> task wb_write;
> input a;
> output reg out;
>
> assign out = a;
>
> endtask
> endmodule
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
>
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