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Message
From: DigitalHomeSoutions at cox.net<DigitalHomeSoutions@c...>
Date: Mon Apr 16 15:18:41 CEST 2007
Subject: [oc] Verilog "Task" Help
Help! I've tried everything I can think of to try and get the
Verilog "Task" function to work with ISE but I keep getting errors that
Xilinx is working on the issue or the service pack has the fix (didn't
work).
Can anyone tell me what the correct format is for using the "Task"
function in ISE? Here is what I have so far:
module Controller(
input clk,
output reg wb_dat_o);
always begin
wb_write(clk, wb_dat_o);
end
task wb_write;
input a;
output reg out;
assign out = a;
endtask
endmodule
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