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From: richard.hoge at mathstar.com<richard.hoge@m...>
Date: Fri Apr 13 03:08:50 CEST 2007
Subject: [oc] I2C Bit State machine
Operator Error! My application was setting the STA bit for every
operation.

> I am seeing a strange behavior from the state machine in
> I2C_master_bit_ctrl. When I receive the ACK from my external device
> (9th clock cycle), I get a 10th clock pulse, then the machine stops
> in
> IDLE. I see this in simulation and on the hardware. When looking at
> the simulation, the state machine is transitioning through the rd_a
> ->
> . . .->idle steps twice. Should this be happenining?
> I epxected the SCL line to be held (high/low?) until either another
> start or stop. Is this correct?
> Thanks!
>
>