|
Message
From: Matt Ettus<matt@e...>
Date: Thu Apr 12 04:14:49 CEST 2007
Subject: [oc] Wishbone spec clarification
I have a few questions about the Wishbone specs:
=====================================
The wishbone spec, Rule 3.30, on page 41 states:
SLAVE interfaces MAY NOT respond to any SLAVE signals when [CYC_I]
is negated.
However, in figure A-11 on page 110, it is clear that the CYC_I signal
is completely ignored by the simple register. It also similarly
violates Rule 3.35 on page 41,
The cycle termination signals [ACK_O], [ERR_O], and [RTY_O] must be
generated in response to the logical AND of [CYC_I] and [STB_I].
I'm new to wishbone, so I'm not sure if this is a big deal or not, but I
could imagine problems if the INTERCON assumes the slaves follow these 2
rules and they don't.
======================================
What is the purpose of the LOCK_O signal? From the description it says
that it indicates that the bus cycle is uninterruptible. However, the
statement:
Once the transfer has started, the INTERCON does not grant the bus
to any other MASTER, until the current MASTER negates [LOCK_O] or [CYC_O].
If deasserting CYC_O causes the lock to end, then this signal doesn't
really do anything more than asserting CYC_O by itself, does it?
========================================
What is the cab_i signal on slaves and cab_o on masters which the
wb_conbus uses? I don't see it mentioned anywhere in the specs, and the
conbus just seems to pass it on without acting on it.
========================================
Thanks,
Matt
|
 |
Browse
