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This is a newbie question but why would the waveform not represent the

>  This is a newbie question but why would the waveform not represent the
> the test bench?
A waveform generated from the testbench obviously represents the testbench.
But what's the added value? A testbench that checks itself is much easier
to modify, run, and verify than visually comparing waveforms.
Testbenches without waveforms run an order of magnitude faster than those
dumping waveforms and are portable between simulator platforms. This makes
them the preferred method of verification.

There are many signals in the core, which ones do you want to see? No
matter what answer you provide, it's always the signal not listed that's
the problem.
Watching waveforms is nice if you're debugging a specific section of the
code and you know where to look. But in a system with millions of nets it
can be a nightmare.

My personal approach is to write self checking testbenches. Initially this
takes about 3times as much than writing a simple testbench and checking
the waveforms. However in the end they always prove to be more cost
efficient. Where cost is defined by flexibility, extensibility,
portability, system run time, and system requirements.
As an example the commercially available i2c master/slave core has a huge
testbench. It runs for 20minutes on my compute server (believe me it's a
very fast machine). With signal dump enabled (i.e. generating waveforms)
it runs for an hour. The resulting signal database is huge.
Now what signal did you want to compare???

I hope this explains ...

Richard

--- On Tue 04/03, &lt; richard@h... &gt; wrote:
> From: [mailto: richard@h...]To: cores@o...: Wed, 4
> Apr 2007 03:13:37 +0200 (CEST)Subject: Re: [oc] I2C IssueHi guys,The
> provided testbench works; it has been tested on synopsys vcs,
> cadencencsim, and modelsim. These are the 3 leading simulators.The core
> works; I have confirmed reports of over 50 companies using thecore in
> their designs; a few more if you add those companies using thecommercially
> available versions. And it works out of the box!!!I added a makefile (for
> ncsim only) that runs the testbench.Combining the core (in rtl), the
> testbench (in bench), the makefile (insim/bin), and the documentation (in
> doc) you should be able to get thisrunning. Ok admitted you need to
> understand the wishbone bus interface; sodownload that spec too.I heard
> complaints about the doc, people not being able to find thetestbench,
> people not being able to hook everything together.To be honest, this
> indicates either a lack of knowledge of using IP cores(which is fine, but
>
> then don't blame the core), or just a general lazynessin searching
> opencores.The testbench is self checking; this means it is not waveform
> oriented.Forget about checking waveforms with your eyes. This might work
> for thei2c interface but not for bigger IP cores. Instead the testbench
> initiatestransfers and automatically checks the core (i.e. the status of
> the i2cbus and registers). Obviously the testbench does wiggle the sda and
> scllines ;)Down to the stupid questions;1) Did you run the provided
> testbench or are your running your own?2) Did you create the open-drain
> outputs using the tri-state buffers asdescribed in the doc. Please don't
> tell me you don't understand the doc asit provides a graphical
> representation and the actual code to implementthe buffers (both in vhdl
> and verilog).3) Did you pull-up SDA and SCL in the testbench?Some notes:1)
> There is a typo in the VHDL code; scl_pad_i &lt;= sda should of course
> besda_pad_i &lt;= sda. But you should have figured that out.2)
> No idea why there's still a documentation folder. It should be
> removed.Richard&gt; I'm getting the same problem that DR is getting. SDA
> and SCL are not&gt; toggling. Has anyone been able to get it to work or is
> this how the test&gt; bench works? Richard has done a great job putting
> this together, I just&gt; wish he would've included an explicit readme
> file and a simulation result&gt; for reference.&gt; Steve&gt;
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