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Message
From: richard at herveille.net<richard@h...>
Date: Mon Mar 26 15:54:06 CEST 2007
Subject: [oc] I2C Open Drain VHDL Implementation
> I'm still working on getting the I2C core working but I'm a little bit
> confused. It probably is simple but I can't figure it out. How do I
> implement the open drain
Please follow the guidelines in the documentation. There are graphical,
verilog, and vhdl examples.
Just copy and paste the code.
> and how is the line pulled to VCC?
The line is pulled up to VCC by the external resistor.
The I2C bus implements a wired OR on it's lines.
In VHDL you have to simulate this in your testbench by driving SDA and SCL
to 'H'.
> I've figured
> out how to do it in the schematic layout but I'm not sure on the VHDL
> side. How does the open-drain relate to the tri state buffer?
The tri-state implements the open drain.
Basically an open drain is capable of pulling a line low, but not high.
The same functionality is achieved by using a tri-state buffer that, when
enabled, pulls the line low.
scl <= '0' when scl_oen else 'z'.
assign scl = scl_oen ? 1'b0 : 1'bz.
Richard
> Any help would be greatly appreciated.
> Thanks,
> DR
>
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