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Message
From: Mikhail Matusov<misoma@r...>
Date: Sat Mar 24 01:08:33 CET 2007
Subject: [oc] Using Wishbone bus in Xilinx EDK
You need to design or find a bus bridge, e.g. OPB-to-Wishbone, or
PLB-to-Wishbone.
/Mikhail
On Sat, 24 Mar 2007 02:58:20 +0100 (CET)
Karim Ali <khadgar34+opencores@g...> wrote:
> Hi,
>
> I am a beginner developer using XPS with one of the Xilinx Virtex 2
> Pro FPGA. The board came with a baseline defined by the manufacturer,
> and it uses the Xilinx EDK (Xilinx Platform Studio).
>
> I'm wondering how would I use these open cores that have been
> developed with the Wishbone bus in mind. The Xilinx EDK only has the
> IBM CoreConnect busses for use it seems.
>
> I am currently trying to use the UART 16550 core on this site, and I
> don't know how to access it through the software in my projects.
>
> Any help is appreciated
>
> Karim
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
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