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Message
From: vax11780 at porky.vax-11.org<vax11780@p...>
Date: Fri Mar 23 04:23:30 CET 2007
Subject: [oc] new to cores world, need a little help
This is correct, the sci and scl signals are defined as open collector
(or open drain) outputs. You need to have external pullups to make
it work.
In verilog you can use the pullup/pulldown primitives. In VHDL I think you
have to have a weak driver in your testbench.
Clint
On Thu, 22 Mar 2007, D R wrote:
> I believe I've found the problem. At the bottom of the "i2c_master_bit_ctrl.vhd,v 1.14 2006/10/11" scl and sda are assigned 0 and I can't find anywhere else that the they are updated. Has anyone come up with a fix for this?Thanks,DR -- assign outputs scl_o <= '0'; scl_oen <= iscl_oen; sda_o <= '0'; sda_oen <= isda_oen;--- On Thu 03/22, D R < heedaf@e... > wrote:From: D R [mailto: heedaf@e...]To: cores@o...: Thu, 22 Mar 2007 14:05:13 -0400 (EDT)Subject: Re: [oc] new to cores world, need a little help
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> Hase anyone tried using the I2C Core with Xilinx’s ISE? I’ve found a problem with my project using this core. When I back trace the sci and scl outputs in the generated schematic they are not connected to ground. This would explain why the outputs aren’t working. Any idea what may cause this problem?
> Thanks,
> DR
>
>
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