LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cores > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: Mark McDougall<markm@v...>
    Date: Mon Mar 19 02:47:32 CET 2007
    Subject: [oc] I2C FPGA Inputs
    Top
    heedaf@e... wrote:

    > I’m not sure what “wb_adr_i” is for. Definition
    > says it is “Lower address bits” but I’m not sure why this would be
    > required. I’m also a little confused on “wb_we_i” and “wb_stb_i” and
    > what their purpose is for. Please forgive me if these are dumb questions
    > but I sure would appreciate the help.

    Read the wishbone bus specification.
    <http://www.opencores.org/projects.cgi/web/wishbone/wishbone>

    Regards,

    --
    Mark McDougall, Engineer
    Virtual Logic Pty Ltd, <http://www.vl.com.au>
    21-25 King St, Rockdale, 2216
    Ph: +612-9599-3255 Fax: +612-9599-3266

    ReferenceAuthor
    [oc] I2C FPGA InputsHeedaf

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.