OPENCORES.ORG

manuel.kampert at online.de wrote:

The core that i've used was
http://www.opencores.org/pdownloads.cgi/list/a_vhd_16550_uart
Unfortunately it did not contain any testbench.
----- Original Message ----- 
From: Günter Dannoritzer<dannoritzer@w...> 
To: 
Date: Fri Mar  9 14:00:39 CET 2007 
Subject: [oc] Serial / UART link to host 

> manuel.kampert at online.de wrote: 
> > Hello! 
> [...] 
> > I choosed the VHDL USART circuit from this forum and read the 
> > documentation. I was quite impressed about the complexity of 
> this 
> > module and was unable to figure out how to just send some 
> single bytes 
> > to my machine. 
> > 
> Maybe I overlooked one, but do you mean the 
> Serial UART 
>  http://www.opencores.org/projects.cgi/web/uart 
> or the 
> UART 16550 
>  http://www.opencores.org/projects.cgi/web/uart16550 
> The first one has a VHDL testbench, the later one only a Verilog 
> one. If 
> there is nothing in the documentation, the test bench might be the 
> best 
> place to look how they feed data into the core. 
> Cheers, 
> Guenter 
> > Does someone have some lines of code that would give me a 
> start to 
> > initialize this circuit? 
> > 
> > Many Thanks, 
> > Manue. 
> > _______________________________________________ 
> > http://www.opencores.org/mailman/listinfo/cores 
> > 
> 
>