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Message
From: larytet.46060479 at bloglines.com<larytet.46060479@b...>
Date: Tue Feb 20 14:01:50 CET 2007
Subject: [oc] data base for ASIC/FPGA develpers
Our typical ASIC is 4-20K bytes of registers.
Development time of the ASIC
is 0.5-1.5 years.
I think that SQL data base is inevitable.
The team is
15 designers and verification engineers, may be 10 software guys.
XML
document is limited by the flexibility of the
version manager and tools
to render the file.
mySQL apparently supports log, rollback and backup
(I still investigate it)
Indeed ability to compare different versions
of
the file sounds great, but the file itself is
going to be huge. For example,
file containing
macros for the software guys is above 50K lines.
Data sheet
describing the registers exceeds 1000
pages. We really need some data base
and
concurrent access to the data base. SQL sounds a
like a natural choice.
I do not know how unique our problem is.
>From the answers I see that
some cos do use
tools like the one I described. Still there is no
anything
customizable enough to fit anybody.
I will probably go forward with the
project. If
you think you could switch to it in the future
from the proprietary/commercial
solutions - this
is the right time to try to define system
requirements.
greatly appreciating all answers and comments
thank you
>I authored
something similar many years ago. It
>was used to generate
>C/C++ defines
and functions/macros/structures
>for register and
>bitfield access. It
also had a searchable web
>frontend and the ability
>to annotate test vectors.
I took it one step
>further and actually
>generated the Verilog code for
the register
>interface modules from the
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