LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cores > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: Gunnar Dahlgren<gunnar.dahlgren@a...>
    Date: Tue Feb 20 11:31:33 CET 2007
    Subject: [oc] data base for ASIC/FPGA develpers
    Top
    Sounds similar to RDL, see:
    http://www.eetimes.com/news/design/showArticle.jhtml?articleID=181503390

    If I got it right, the RDL language is open but the "Denali Blueprint"
    compiler is a commercial product.

    I haven't used RDL but we use a similar in-house-developed system, which
    I find invaluable.

    Regards
    Gunnar Dahlgren

    Jeremy Fillingim wrote:
    > I authored something similar many years ago. It was used to generate
    > C/C++ defines and functions/macros/structures for register and
    > bitfield access. It also had a searchable web frontend and the ability
    > to annotate test vectors. I took it one step further and actually
    > generated the Verilog code for the register interface modules from the
    > same database, that way I would be sure that the software, hardware ,
    > and documentation were all in sync at any moment in time.
    >
    > Honestly, rather than a SQL database, you might want to consider
    > something a little lighter weight that is more easily version
    > controlled. I chose to use a simple XML document (any simple markup
    > would have worked) and found that it worked quite well.
    >
    > As an ASIC designer who also writes drivers for the hardware, I found
    > the tool to be indispensable, and so did the other 25 members of my
    > team (hardware and software alike).
    >
    > On 2/20/07, Richard Tierney <rt-opencores@c...> wrote:
    >> I had a quick look through your doc and, with the best will in the
    >> world, I can't see that this would be of any use at all. There isn't any
    >> feature in it that made me stop and think "wow, that's something I/We
    >> could really have used on a project".
    >>
    >> What's the point? Have I missed something? At first sight, this looks a
    >> spec whose sole purpose is to waste time and money.
    >>
    >> /RT
    >> _______________________________________________
    >> http://www.opencores.org/mailman/listinfo/cores
    >>
    > _______________________________________________
    > http://www.opencores.org/mailman/listinfo/cores

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.