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    Navigation: All forums > Cores > Message List > Message Post

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    From: dhineshbalu at gmail.com<dhineshbalu@g...>
    Date: Tue Feb 13 12:59:38 CET 2007
    Subject: [oc] TLB Design
    Top

    ----- Original Message -----
    From: deepak_patnaik@h...
    To: cores@o...
    Date: Tue, 5 Mar 2002 13:55:53 +0100
    Subject: Re: [oc] TLB Design

    >
    >
    >
    > u plz suggest the method of how to implement CAM specifically in
    > vhdl/verilog.
    > ----- Original Message -----
    > From: Ali Mashtizadeh <ali@a... >
    > To: cores@o...
    > Date: Tue, 26 Feb 2002 18:00:48 -0800
    > Subject: [oc] TLB Design
    > we need aprogram for network protocol using vhdl program
    > >
    > >
    > > Well I understand that I am supposed to use a state machine to
    > do
    > > the
    > > comparisons. It's like this
    > >
    > > virtual Address->[Content Addressable Memory(State
    > > machine)]->[RAM]->Physical Address
    > >
    > > The CAM(Content Addressable Memory) is my problem. You need to
    > use
    > > a
    > > state machine to do the comparisons but that means if you have
    > a 64
    > > entry tlb then it will take 64 clock cycles. Unless you make
    > the
    > > state
    > > machine's clock to be 64 times faster. I understand that most
    > cpu's
    > > break up the process into several smaller blocks of 4 or 8
    > entries
    > > and a
    > > seperate comparator for each block but still that means I have
    > to
    > > use up
    > > my precious DLL's. As for a TLB compatible with a 386 your
    > gonna
    > > have
    > > fun with that. You need to make a search state machine to find
    > > entries
    > > out of the page tables when it is not in the TLB cache.
    > >
    > > You can simplify your TLB by using a direct mapped cache. But
    > thats
    > > not
    > > too nice. (IE: you hash(in some way or form) the virtual
    > address
    > > and use
    > > that as an index pointer. It can be something like the least
    > > significant
    > > bits of the virtual address(ofcourse after the first bits that
    > are
    > > less
    > > than your page size.) I am concidering that method since its
    > > simpler. I
    > > personally will use several parrallel direct mapped caches so
    > that
    > > to
    > > addresses with the same hash can exists on my tlb at the same
    > time.
    > >
    > > Can someone tell me what they have done for their TLBs?
    > >
    > > Ali
    > >
    >

     
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