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Message
From: Richard Tierney<rt-opencores@c...>
Date: Thu Feb 8 22:39:26 CET 2007
Subject: [oc] Async reset: active high or active low?
Guy Hutchison wrote:
> As I recall from my (distant) board design days, the main reason for
> having an active-low reset is that it's easier to keep the reset
> asserted low during board power-on than to keep it high. Makes no
> difference for on-chip resets, though, since it's easy enough to invert
> when it comes on chip...
On 5V TTL designs, there's better noise margin on high levels, so it
could occasionally make sense to have active-low signals. It makes no
difference at all with CMOS. The OP should look at some CMOS I/O
structures; they're symmetrical, with high-impedance inputs. I guess
there could be trivial differences related to sizing of N and P channel
transistors, or input protection structures, or excess leakage sub-90nm,
but I've never heard of anyone using that as a basis for selecting a
signal polarity.
Amazing how a thread can go on for 3 years here... :)
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