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He's right. There will be current drain between the high signal and

Can you defend this position with numbers?
there is lots of stuff connected to VDD in silicon that a low reset 
could leak to that  you may be ignoring.

john

dude@s... wrote:
> He's right.  There will be current drain between the high signal and 
> ground which is a waste.
> 
> ----- Original Message ----- 
> From: Rudolf Usselmann <rudi@a...> 
> To: cores@o... 
> Date: 27 Apr 2003 15:33:27 +0700 
> Subject: Re: [oc] Async reset: active high or active low? 
> 
>>
>> On Sun, 2003-04-27 at 14:48, Haytham Azmi wrote: 
>>> Hi Nicolas , 
>>>            I don't agree with you , i think it must be active 
>> high for 
>>>            many reasons .. 
>>>            1- At power up it's normal for all system to reset 
>> , this is 
>>>               the normal case and then , start executing the 
>> main 
>>>               program . 
>>>            2- If we put the reset active low , that means you 
>> have to 
>>>               put high at the reset signal during normal mode 
>> , and 
>>>               that will be a sourcefor power loss ... so it's 
>> better 
>>>               to make it active high . 
>> Hugh ? Source for power loss ? 
>>
>> Not if you designing in CMOS. It "consumes" power 
>> when it switches from one level to the other. If 
>> you do not switch (change logic levels) power 
>> consumption should be very close to zero (in any 
>> practical terms anyway). 
>>
>>>            3- I think you can check for any microcontrolle 
>> datasheet 
>>>               you will see that the reset is active high . 
>>>
>>>               If iam wrong please correct my information. 
>>>
>>>                                                   Best 
>> redards, 
>>>                                                      Haytham 
>> In my opinion it should be absolutely irrelevant if reset 
>> is active high or low. Use an inverter - the synthesis tool 
>> might turn the level around anyway, because of your synthesis 
>> library constrains (e.g. only active low asycn reset flops 
>> are available) and insert an inverter if it needs to. 
>>
>> For IP cores that you want to be used/re-used by others I have 
>> two suggestions: 
>>
>> 1) Make the Level of the reset user selectable: 
>>
>> for example: 
>>
>> `define ACT_RST_LEVEL 1'b1   // Active HIGH 
>> `define ACT_RST_LEVEL 1'b0   // Active LOW 
>>
>> always @(posedge clk) 
>> 	if(my_reset == `ACT_RST_LEVEL)	my_flop <= 1'b0; 
>> 	else				my_flop <= din; 
>>
>>
>> 2) Make the type of the reset (sync/async) also user selectable: 
>>
>> for example: 
>>
>> `define ACT_RST_LEVEL 1'b1   // Active HIGH 
>> `define ACT_RST_LEVEL 1'b0   // Active LOW 
>>
>> `define ASYNC_RST or posedge my_reset	// Asynchronous High Active 
>> `define ASYNC_RST or negedge my_reset	// Asynchronous Low Active 
>> `define ASYNC_RST			// Synchronous Reset 
>>
>> NOTE: Make sure ACT_RST_LEVEL matches the async reset definition 
>> !!! 
>>
>> always @(posedge clk  `ASYNC_RST) 
>> 	if(my_reset == `ACT_RST_LEVEL)	my_flop <= 1'b0; 
>> 	else				my_flop <= din; 
>>
>>
>> One of these days I will go through all of my cores and 
>> implement the above in all of them ! 
>>
>> Cheers ! 
>> rudi 
>> ------------------------------------------------------- 
>> www.asics.ws  -- Solutions for your ASIC/FPGA needs --- 
>> ---------------- FPGAs * Full Custom ICs * IP Cores --- 
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>>
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