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Message
From: Flexie at gmx.de<Flexie@g...>
Date: Mon Feb 5 16:41:49 CET 2007
Subject: [oc] CAN Controller
Hi,
I'm using the verilog version of can_top and I fail to read out any
receive data out of can_fifo except for the first message. I am using
extended mode, and i did not forget to set the release buffer bit.
I wonder how the length_info register shall be used.
There is a signal called initialize_memories, its value starts with 1
and wont change until there is a write_info_pointer overrun (since :
if(&write_info_pointer) init_mem <= 0;)
because of this my length info used to be 0 in each register all the
time, which might be the desired result of that memory initialisation.
How do you do that usually when you restart your can controller, do
you send some dummy messages at the start?
I dared to change the after reset value of init_memories from 1 to 0
and I used Model Sim to check the result. In my test, the first
message I write into the fifo has a length of 5 byte (no real message
with id, just simulating the fifo module) and the second one has a
length of 4 byte. The contents of the fifo is expectedly those written
9 bytes and the contents of the length_fifo register is 1st byte: 5,
2nd byte: 4. So far so good, but I dont see how reading out the
messages will work in that case, since the read_info_pointer is
incremented after each clk where there is a release_buffer signal, so
after I read out the first byte of fifo (lets say address 16 which
would be address 0 of fifo) the next read_address will already be
address + 4 (fifo adddress 20+x) and I havent even read the second
byte of the first message (fifo address 17).
Where am I mistaken and how can I manage to read out the messages one
by one?
Hope anyone can understand my problem.
Thanks for any helpful answer!
Flex
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