LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cores > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: Mike Delaney<mmdst23@g...>
    Date: Thu Dec 28 23:38:07 CET 2006
    Subject: [oc] Query
    Top
    Did you look at Altera's examples for NiosII devices? I'm pretty sure
    they have some decent documentation on it.

    Mike

    On 12/28/06, Ahmed Ben Abdallah <bohmid@g...> wrote:
    > Hi every body i'm a hardware engineer and i have been graduated this year
    > (June 2006)
    > I have have conceived some copressor (Hardware accelerator) written in VHDL
    > language fo the 3D algorithm and i have interfaced this accelerator with
    > NiosII processor as custom instructions. The result is up to 60 % speed up
    > compared with the software version.
    >
    > Actually, i'm working on constructing a bridge and i really need some help
    > especially for the Avalon bus.
    > So can someone send me some samples or model of bridge written in VHDL
    > language.
    > I will very grateful to him and i will share with him some of my previous
    > work .
    > Best regards
    >
    >
    >
    >
    > 2006/12/28, johan.wouters@e... <johan.wouters@e... >:
    > > Hi Preethi,
    > >
    > > It seems you are mixing 2 things: hardware design (VHDL/Verilog) and
    > > software design (C/C++/...).
    > >
    > > Stating that you use an ATMEL processor suggests that you want to be
    > > looking at software languages and embedded operating systems instead
    > > of HDL's.
    > > Or, could it be that you use an embedded processor core in a SoC and
    > > that you are looking for (opencores) IP cores to put on the bus? In
    > > this case you might be looking for information or help to construct a
    > > bridge from the ATMEL bus to something like the Wishbone SoC bus. This
    > > would be done in VHDL or Verilog.
    > >
    > > kind regards,
    > > Johan
    > >
    > > ----- Original Message -----
    > > From: chellam1005 at yahoo.co.in<chellam1005@y...>
    > > To:
    > > Date: Thu Dec 28 09:35:30 CET 2006
    > > Subject: [oc] Query
    > >
    > > > iam working on GPS based system.
    > > > iam using a 32 bit processor from atmel.
    > > > how to program the processor using VHDL;also how to obtain GUI in
    > > > VHDL?
    > > > pls do the needful.
    > > > regards,
    > > > preethi
    > > >
    > > >
    > > _______________________________________________
    > > http://www.opencores.org/mailman/listinfo/cores
    > >
    >
    >
    > _______________________________________________
    > http://www.opencores.org/mailman/listinfo/cores
    >
    >

    ReferenceAuthor
    [oc] QueryAhmed Ben Abdallah

    Follow upAuthor
    [oc] QueryAhmed Ben Abdallah

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.