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    From: Shekhalev Denis<Denis.Shekhalev@e...>
    Date: Fri Dec 22 08:49:33 CET 2006
    Subject: [oc] 1. Re: About Open Source VLIW core (dannoritzer)
    Top

    Hello!

    I have greate interest in microprogramming unit (like sequencers and processors) realisation based om FPGA. Especialy I interesting in high-performance microprogramming units.

    I would like to see documentation about VLIW core and maybe take a part in this project, like hardware developer. I have some expirience and some developed units in this theme.

    Denis Shekhalev.

    -----Original Message-----
    From: ------------------------------ _______________________________________________ Cores mailing list ------------------------------ _______________________________________________ Cores mailing list ------------------------------ _______________________________________________ Cores mailing list ------------------------------ _______________________________________________ Cores mailing list ------------------------------ _______________________________________________ Cores mailing list ------------------------------ _______________________________________________ Cores mailing list ------------------------------ _______________________________________________ Cores mailing list ------------------------------ _______________________________________________ Cores mailing list ------------------------------ _______________________________________________ Cores mailing list ------------------------------ _______________________________________________ Cores mailing list Cores@o... cores cores cores cores cores cores cores cores cores cores cores cores cores cores cores cores cores cores cores cores> hi how we split a clock in to subclock (i.e.divided by 2,3, 4) using VHDL. ----- Original Message ----- From: Shehryar Shaheen<shehryar.shaheen@u...> To: Date: Sat May 15 17:10:09 CEST 2004 Subject: [oc] Quick Start on Opensource ASIC design VLSI Tools > Ofcourse the Alliance tools cannot be compared with Synopsys DC > or Cadence Buildgates etc but theses tools have big price tags > which > the Allaince tools don't. Its common knowledge that free tools may > not be wholly at par with the ones that are not free but then this > doesn't mean that nomenclature has to be different > Icarus Verilog is grouped under 'Verilog Simulator' but because > it doesn't have all the features that NC-Verilog or Verilog-XL have > it doesn't need to called say 'half-verilog simulator' or something > , now > does it :) > Alliance tools are free and are opensourse and yes they place > some amount of restrictions as to the way RTL is written but > then RTL is always written with strict rules keeping mind what > the synthesis tools will infer from the RTL. > Even Design Compiler or some other high end (and not free) tools > will not allow for absolute freedom to write what ever construct > one > feels like that is part of VHDL or Verilog language and the > synthesis > tools doesn't complain about it and one still might have to do > changes in the code to get it synthsized. > While they do support a larger synthesizable subset they are > neither free nor opensource. > ----- Original Message ----- > From: "Guy Hutchison" <ghutchis@g...> > To: "Discussion list about free open source IP cores" > <cores@o...> > Sent: Saturday, May 15, 2004 7:17 AM > Subject: Re: [oc] Quick Start on Opensource ASIC design VLSI Tools > > > That essentially IS logic sysnthesis of standard VHDL RTL > > > aftet this you get a VHDL gatelevel netlist made up with > > > standrad cells from the library sxlib ( sxlib is > distributed with > Allance) > > > > Unforunately, neither Verilog nor VHDL has ever defined what > portion > > of the language constitutes the synthesizable subset, and so > we are > > left with de facto standards. The bar for this is whatever > VHDL code > > can be accepted by common synthesis tools as Design Compiler > and > > Get2Chip. While VASY does support more constructs than I > thought it > > did, it was unable to translate several VHDL files (from > > opencores.org) which I have previously compiled with DC. > > > > This means that, in practice, unless you are coding > specifically for > > the Alliance tool set, compiling your code with VASY will > require > > rewriting substantial portions of it. > > > > My comment about being misleading was that if you make a > statement > > like "tool XXX supports logic synthesis" with no > conditions or > > caveats, anyone looking at the tool will expect it to have > roughly the > > same capabilities and limitations of other tools that support > logic > > synthesis; VASY/BOOM does not meet these criteria. > > _______________________________________________ > > http://www.opencores.org/mailman/listinfo/cores > > ------------------------------ Message: 4 Date: Thu, 14 Dec 2006 16:06:50 -0000 From: "Colin Bathe" <colin.opencores.cores@s...> Subject: RE: [oc] Quick Start on Opensource FPGA design VLSI Tools To: "Discussion list about free open source IP cores" <cores@o...> Message-ID: <PHEDLCCPJAKFGPPEHNLDEECAGGAA.colin.opencores.cores@s...> Content-Type: text/plain; charset="iso-8859-1" > hi > > how we split a clock in to subclock (i.e.divided by 2,3, 4) using VHDL. If you can't divide a clock by 2 or 4 then you need to go back to reading VHDL for Dummies as this is very very basic stuff. Dividing a clock by 3 with a 1 to 2 mark to space ratio is also very easy.. Dividing a clock by 3 with a 1 to 1 mark to space ratio is hard and requires use of some VHDL Voodoo. Post back here when you have worked out how to do the easy things and I'll give you some hints on how to this final thing. Colin. ------------------------------ Message: 5 Date: Thu, 14 Dec 2006 21:38:08 +0100 From: Bouygues Telecom <bouygues@i...> Subject: [oc] Remportez un s?jour pour deux ? Hollywood ! To: "cores@o..." <cores@o...> Message-ID: <884a226e0f3bf60a886e9d13b76678ec@l...> Content-Type: text/plain; charset="iso-8859-1" Si vous dИsirez visualiser ce mail au format html, recopiez l'adresse suivante dans votre navigateur: http:///view.html?id=2829&ref=506910 Si vous dИsirez vous dИsinscrire, il suffit de cliquer sur le lien prИvu ou de recopier l'adresse suivante dans votre navigateur: cores@o...&client=31">http:///desabo.html?ope=2829&email=cores@o...&client=31 -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20061214/ff21a747/attachment-0001.html ------------------------------ Message: 6 Date: Sun, 17 Dec 2006 22:20:06 +0100 (CET) From: syuyang@g... Subject: Re: [oc] MP3 Decoder in VHDL To: cores@o... Message-ID: <20061217212006.45EF24C2B0@w...> Hello, I am working on mp3 decoder for my cource project recently. I have surveyed lots of paper, standard about mp3 decoder process, but still didn't know how to implement. Did anyone have the source code in verilog or VHDL, can send to me. That would be very helpful!!! mail:syuyang@g... ----- Original Message ----- From: penny1way<penny1way@y...> To: Date: Wed Sep 13 07:22:44 CEST 2006 Subject: [oc] MP3 Decoder in VHDL > I'm interested in testing your mp3 decoder. Could you please send > me your > source code? > Thanks very much. > Regards, > penny1way > dj_ace_home wrote: > > > > > > Hello, > > I am working on mp3 decoder right now. > > I would really like to have the VHDL mp3 decoder source code > > Thank you very much > > > > > > > > ----- Original Message ----- > > From: linboring at y...<linboring at y...> > > To: > > Date: Wed Apr 28 20:19:31 CEST 2004 > > Subject: [oc] MP3 Decoder in VHDL > > > >> please send me the source core. > >> Thank you very much!!!! > >> ----- Original Message ----- > >> From: lukedarnell at i...<lukedarnell at i...> > >> To: > >> Date: Thu Mar 11 13:14:27 CET 2004 > >> Subject: [oc] MP3 Decoder in VHDL > >> > I would love to have a look at the VHDL mp3 decoder > >> > > >> > ----- Original Message ----- > >> > From: arunhirehal at h...<arunhirehal at h...> > >> > To: > >> > Date: Thu Mar 11 05:23:02 CET 2004 > >> > Subject: [oc] MP3 Decoder in VHDL > >> > > please send me the SOURCE CODE OF MP3 DECODER > >> > > > >> > > ----- Original Message ----- > >> > > From: resaka at m...<resaka at m...> > >> > > To: > >> > > Date: Wed Mar 10 16:36:52 CET 2004 > >> > > Subject: [oc] MP3 Decoder in VHDL > >> > > > ----- Original Message ----- > >> > > > From: fanj at i...<fanj at i...> > >> > > > To: > >> > > > Date: Tue Dec 30 08:17:11 CET 2003 > >> > > > Subject: [oc] MP3 Decoder in VHDL > >> > > > > could you send me your cores please? > >> > > > > > >> > > > > fanj at i... > >> > > > > > >> > > > > ----- Original Message ----- > >> > > > > From: duan at u... > >> > > > > To: cores at o... > >> > > > > Date: Tue, 16 Dec 2003 01:39:28 +0100 > >> > > > > Subject: [oc] MP3 Decoder in VHDL > >> > > > > > > >> > > > > > > >> > > > > > Hi all, > >> > > > > > > >> > > > > > We have completed a project of > MP3 Decoder > >> in > >> > VHDL > >> > > for a > >> > > > > course. If > >> > > > > > anyone is interested in it, > please send us > >> > email. We > >> > > can > >> > > > send > >> > > > > you > >> > > > > > the > >> > > > > > source codes. > >> > > > > > > >> > > > > > Regards, > >> > > > > > Kevin > >> > > > > > > >> > > > > > >> > > > > Hi, i'm working on a encoder/decoder > for MP3 > >> and i'm > >> > very > >> > > > interested > >> > > > in test your source codes. > >> > > > Thanks, > >> > > > Isaac > >> > > > > >> > > > > >> > > > >> > > > >> > > >> > > >> > >> > > _______________________________________________ > > http://www.opencores.org/mailman/listinfo/cores > > > > > -- View this message in context: > http://www.nabble.com/Re%3A-MP3-Decoder-in-VHDL- tf641130.html#a6279246 > Sent from the OpenCores - IP Cores forum at Nabble.com. > ------------------------------ Message: 7 Date: Thu, 21 Dec 2006 02:06:09 -0800 (PST) From: djo8070 <wajdi.benhmida@g...> Subject: Re: [oc] MP3 Decoder in VHDL To: cores@o... Message-ID: <8005460.post@t...> Content-Type: text/plain; charset=us-ascii syuyang wrote: > > Hello, > I am working on mp3 decoder for my cource project recently. > I have surveyed lots of paper, standard about mp3 decoder process, > but still didn't know how to implement. > Did anyone have the source code in verilog or VHDL, can send to me. > That would be very helpful!!! > mail:syuyang@g... > > > ----- Original Message ----- > From: penny1way<penny1way@y...> > To: > Date: Wed Sep 13 07:22:44 CEST 2006 > Subject: [oc] MP3 Decoder in VHDL > >> I'm interested in testing your mp3 decoder. Could you please send >> me your >> source code? >> Thanks very much. >> Regards, >> penny1way >> dj_ace_home wrote: >> > >> > >> > Hello, >> > I am working on mp3 decoder right now. >> > I would really like to have the VHDL mp3 decoder source code >> > Thank you very much >> > >> > >> > >> > ----- Original Message ----- >> > From: linboring at y...<linboring at y...> >> > To: >> > Date: Wed Apr 28 20:19:31 CEST 2004 >> > Subject: [oc] MP3 Decoder in VHDL >> > >> >> please send me the source core. >> >> Thank you very much!!!! >> >> ----- Original Message ----- >> >> From: lukedarnell at i...<lukedarnell at i...> >> >> To: >> >> Date: Thu Mar 11 13:14:27 CET 2004 >> >> Subject: [oc] MP3 Decoder in VHDL >> >> > I would love to have a look at the VHDL mp3 decoder >> >> > >> >> > ----- Original Message ----- >> >> > From: arunhirehal at h...<arunhirehal at h...> >> >> > To: >> >> > Date: Thu Mar 11 05:23:02 CET 2004 >> >> > Subject: [oc] MP3 Decoder in VHDL >> >> > > please send me the SOURCE CODE OF MP3 DECODER >> >> > > >> >> > > ----- Original Message ----- >> >> > > From: resaka at m...<resaka at m...> >> >> > > To: >> >> > > Date: Wed Mar 10 16:36:52 CET 2004 >> >> > > Subject: [oc] MP3 Decoder in VHDL >> >> > > > ----- Original Message ----- >> >> > > > From: fanj at i...<fanj at i...> >> >> > > > To: >> >> > > > Date: Tue Dec 30 08:17:11 CET 2003 >> >> > > > Subject: [oc] MP3 Decoder in VHDL >> >> > > > > could you send me your cores please? >> >> > > > > >> >> > > > > fanj at i... >> >> > > > > >> >> > > > > ----- Original Message ----- >> >> > > > > From: duan at u... >> >> > > > > To: cores at o... >> >> > > > > Date: Tue, 16 Dec 2003 01:39:28 +0100 >> >> > > > > Subject: [oc] MP3 Decoder in VHDL >> >> > > > > > >> >> > > > > > >> >> > > > > > Hi all, >> >> > > > > > >> >> > > > > > We have completed a project of >> MP3 Decoder >> >> in >> >> > VHDL >> >> > > for a >> >> > > > > course. If >> >> > > > > > anyone is interested in it, >> please send us >> >> > email. We >> >> > > can >> >> > > > send >> >> > > > > you >> >> > > > > > the >> >> > > > > > source codes. >> >> > > > > > >> >> > > > > > Regards, >> >> > > > > > Kevin >> >> > > > > > >> >> > > > > >> >> > > > > Hi, i'm working on a encoder/decoder >> for MP3 >> >> and i'm >> >> > very >> >> > > > interested >> >> > > > in test your source codes. >> >> > > > Thanks, >> >> > > > Isaac >> >> > > > >> >> > > > >> >> > > >> >> > > >> >> > >> >> > >> >> >> >> >> > Hello, >> > I am working on mp3 decoder right now. >> > I would really like to have the VHDL mp3 decoder source code >> > Thank you very much > wajdi.benhmida@g... >> > _______________________________________________ >> > http://www.opencores.org/mailman/listinfo/cores >> > >> > >> -- View this message in context: >> http://www.nabble.com/Re%3A-MP3-Decoder-in-VHDL- > tf641130.html#a6279246 >> Sent from the OpenCores - IP Cores forum at Nabble.com. >> > _______________________________________________ > http://www.opencores.org/mailman/listinfo/cores > > -- View this message in context: http://www.nabble.com/Re%3A-MP3-Decoder-in-VHDL-tf2836343.html#a8005460 Sent from the OpenCores - IP Cores mailing list archive at Nabble.com. ------------------------------ Message: 8 Date: Thu, 21 Dec 2006 19:40:54 +0900 From: "Ben A. Abderazek" <ben@i...> Subject: [oc] Crossbar Switch in Verilog HDL To: <cores@o...> Message-ID: <005b01c724ec$7dcd5940$9c4315ac at BENHOASM19WFTF> Content-Type: text/plain; charset="iso-2022-jp" Hello: I am looking for a crossbar switch core (processor) design in verilog HDL.. Specification: 5x5 with input or output buffering. Would you please point me to some papers or source code link. Thanks a lot Ben -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20061221/764bf8c0/attachment.html ------------------------------ _______________________________________________ Cores mailing list Cores@o... http://www.opencores.org/mailman/listinfo/cores End of Cores Digest, Vol 37, Issue 2 ************************************

     
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