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Message
From: Richard Herveille<richard@h...>
Date: Tue Nov 21 16:31:39 CET 2006
Subject: [oc] Suggested extension to wishbone bus
How do you figure it increases performance? If device A is reading device
B, can device C also write to it?
[rih] That's the basic idea
Not many cores support concurrent access
[rih] Fully agreed, therefore most cores will be non Wishbone Duplex core.
But those few that benefit from the enhanced bus structure can use it.
nor do typical bus structures. Are you implying a cross bar type
functionality where device C would write to device D while A is reading B?
[rih] That's up to the system architect. Wishbone does not specify the bus
interconnect. It merely specifies the basic bus architecture.
What kind of interconnect (x-bar, mux, ...) is used is up to the system
architect.
Richard
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