|
Message
From: Mark McDougall<markm@v...>
Date: Thu Oct 26 09:55:45 CEST 2006
Subject: [oc] which the RTL code of I2C core is corrected
Richard Herveille wrote:> Anyways it's always a good idea to thoroughly check whatever IP you receive.
Can't I just put your email and phone number in the code??? ;)
Speaking of testing, I've run into a problem simulating the VHDL core in
my testbench and am wondering why the supplied testbench doesn't have
the same problem (I haven't run it myself as yet)!?!
Using pullups in the top level (verilog) module, the core fails in
i2c_master_bit_ctrl.vhd...
gen_dout: process(clk)
begin
if (clk'event and clk = '1') then
if (sSCL = '1' and dSCL = '0') then
dout <= sSDA;
end if;
end if;
end process gen_dout;
...because sSCL is 'H' rather than '1'...
I've modified...
sSCL <= scl_i;
sSDA <= sda_i;
to
if scl_i = '0' then
sSCL <= '0';
else
sSCL <= '1';
end if;
if sda_i = '0' then
sSDA <= '0';
else
sSDA <= '1';
end if;
... so I can at least simulate it, and it all works.
Regards,
--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
|
 |
Browse
