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Message
From: Nikolaos Kavvadias<nkavv@p...>
Date: Fri Oct 20 17:06:41 CEST 2006
Subject: [oc] synthesizable divider
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"divgen" could be worth to check:
Description (theirs): Divgen is a "divider generator". It generates
optimized and synthesizable VHDL descriptions of hardware division
units. Various algorithms, representations, radices, optimization
parameters and target constraints are supported. Integer and
fixed-point divider unit are supported.
http://lipforge.ens-lyon.fr/www/divgen/
xiaodongjin@h... wrote:
> hello, Currently I am working on a project that needs division
> algorithm, but i have no idea about it, how can i implement a
> synthesizable divider using vhdl or verilog? Would you like to give
> me some kinds of example?
>
> thanks a lot!
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