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    Navigation: All forums > Cores > Message List > Message Post

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    From: chitra_devi84 at yahoo.com<chitra_devi84@y...>
    Date: Thu Sep 14 13:46:36 CEST 2006
    Subject: [oc] An FPGA Implementation Question
    Top

    Hi,
    I need a verilog code for 7_bit LFSR generating odd parity sequence.Kindly send
    me the same.

    Follow upAuthor
    [oc] An FPGA Implementation QuestionGuy Hutchison

     
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