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From: Matthias Mack<MAMACK@g...>
Date: Tue May 30 10:49:41 CEST 2006
Subject: [oc] CAN Protocol Controller: CAN Receive FIFO
Hello All,
I designed the CAN Protocol Controller into a Cyclon II device. The integration runs quite good and after few days I got the first results. All needed baudrates are running also.

During the final tests, I figured out that there are some problems coming up at high bus load. If the current message is not read out before the next one were received, the new one should be stored in the FIFO receive buffer. This works until the FIFO is full. After that there is a big mishmach regarding IDs and data.

I tried to compile with registers and with ALTERA RAM different times, but the results are always equal.

Did sombody know this problem?
Is there any workaround?

Thanks for your help

Matthias Mack

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