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Message
From: Jörn Henneberg<joern.henneberg@a...>
Date: Mon Apr 10 17:14:50 CEST 2006
Subject: [oc] SDRAM CORE by altera
Hi Stefan,you are not talking about the Altera SDRAM Controller Reference Design,
are you?
If so, just leave your hands from this. It does not implement all SDRAM
commands,
introduces large delays, does not support command nesting and so on...
its just
a reference design.
Best regards,
Joern
Stefan Zorn schrieb:
>
> Hello Everybody!
>
> I try to set up the SDRAM CORE from Altera, wich is free with Quartus
> 5.1. For simulation the autogenerated test bench includes a memory
> model by altera. It gets, while initializing, start values from a
> file named sdram_0.dat. Sadly this file is empty. Does anybody know,
> how to wright such a file, or has one for me?
>
> Best Regards
>
> Stefan
>
>
> _______________________________________________
> joern.henneberg.vcf
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