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Message
From: tullio.grassi at reicom.it<tullio.grassi@r...>
Date: Fri Apr 7 15:45:59 CEST 2006
Subject: [oc] simple_spi core questions
I have a few questions about the core simple_spi_top.v
>From line 267 there is:
begin
bcnt <= #1 3'h7; // set transfer counter
treg <= #1 wfdout; // load transfer register
sck_o <= #1 cpol; // set sck
if (~wfempty) begin
wfre <= #1 1'b1;
state <= #1 2'b01;
if (cpha) sck_o <= #1 ~sck_o;
end
end
This is inside an always.
Here sck_o is assigned twice with two concurrent statements.
Is this correct and unambiguous ?
In Verilog all statements in a begin/end block are executed in parallel.
So I guess that when the "if" conditions are true, it is undetermined
which statement will be implemented by the synthsizer.
There is a similar problem in the same module:
the signals wfre and rfwe are assigned twice with two concurrent
statements.
Comments ?
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