|
Message
From: H. Peter Anvin<hpa@z...>
Date: Sun Mar 12 03:34:20 CET 2006
Subject: [oc] Status of TV80
Guy Hutchison wrote:
> On 12/13/05, *H. Peter Anvin* <hpa@z... <mailto:hpa@z...>> wrote:
>
> Sorry... didn't see the message until now.
>
> The problem is that if the test passes, the timing is 10 cycles
> (presumably 4/3/3, like JP.)
>
>
> Could you download a new version of the core and check this again? I
> can't point to anything that has changed, but in my tests I see JR
> having 4/3/5 timing on pass and 4/3 timing on fail.
>
> I have added a simple test (jr1.asm) that performs a number of jump
> pass/fails, if you want to check for yourself.
>
Hi Guy,
I finally got a chance to do this. The JR bug seems indeed to be fixed,
but:
a. I had to add the RETI# extension manually; this is checked into your
tree on the "hpa1" branch but was never merged. What's perhaps more
concerning is that interrupts seem to be screwy -- this could have
something to do with RETI# not working right when I tried to put it back
in. I haven't delved too deeply into this problem yet.
b. I still need a tv80se (with clock enable) top level. Creating one in
the obvious way (just hooking up the cen port on tv80_core) didn't work
-- the CPU ran fine as long as the clock was already enabled, but it
crashed as soon as the clock enable was stopped.
-hpa
|
 |
Browse
