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Message
From: r.p.van.cauter at freeler.nl<r.p.van.cauter@f...>
Date: Mon Feb 27 16:29:55 CET 2006
Subject: [oc] DDR SDRAM Question
Hi Shehryar,I suppose that you are refering to the
http://www.opencores.org/projects.cgi/web/ddr_sdr/overview
core. I only looked at the key features on that page and it indeed
mentions unidirectional DQS support (write only). This is NOT uncommon
for FPGA DDR interfaces, though I also find this a pitty. The truth
is.....the read for a DDR interface and using the DQS is really the pain of
making a decent DDR interface.
It is also possible to perform reads without using the DQS by simply
using the relation between the CK, /CK and the read data. The FPGA
clocks in the data often by using a phase shifted version of the CK,/CK
clock. So it can work, but closing the timing requirements (including the
PCB trace length requirements) is more difficult and therefore often
slower.
Best regards,
Ralph
----- Original Message -----
From: Shehryar Shaheen<shehryar.shaheen@u...>
To:
Date: Sun Feb 26 14:26:03 CET 2006
Subject: [oc] DDR SDRAM Question
> Hello ,
> Had a question on the DDR SDRAM controller
> The 'dqs_q' port of the controller is 'out' only , so how does the
> controller perform read
> operations as the DQS ( or data strobe ) is genrated by the DDR
> SDRAM device for reads and
> for writes the memory controller generates the DQS
> The DQS port should be 'inout' ( 'in' for reads and 'out' for
> writes ) or maybe I'm missing something.
> If any user or the Author himself can answer , I'll appriciate.
> Best Regards
> Shehryar
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