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From: jdemane at rivulet.com<jdemane@r...>
Date: Fri Jan 20 14:01:43 CET 2006
Subject: [oc] Synthesable SPI slave model?
Hi,

Did you ever find a spi slave core? I need one, too.

Regards, Janet

----- Original Message -----
From: real_joenet@h...<real_joenet@h...>
To:
Date: Mon Jan 12 09:32:12 CET 2004
Subject: [oc] Synthesable SPI slave model?

> I'm new in verilog/VHDL
> Would you anybody teach me where can I get a free SPI slave verilog
> code?
> I have already tried to do systhesis for Simon's SPI slave model on
> OpenIPCore. And I used FPGAadv5.3(Altera and other devices by
> LeonardoSpectrum) to do it, but it said that it was NOT synthesable
> with the following message; "Illegal expression in even
> control"
> its corresponding verilog code is the following
> ------------------------------------------------------------
> always @(posedge(sclk && !rx_negedge) or negedge(sclk
> &&
> rx_negedge) or rst)
> ------------------------------------------------------------
> What's wrong with me? or Could you teach me where can I get fully
> synthesable SPI master/slave core with testbench code?
> Thanks
>
>