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Message
From: hbollon at yahoo.fr<hbollon@y...>
Date: Wed Jan 4 18:40:19 CET 2006
Subject: [oc] Wishbone in UART16550
Hello Francis,
I search UART16550 vhdl model of verilog Opencores model.
Do you if anybody have this model ?
Thanks in advance
Henri
----- Original Message -----
From: Ielsch Francis<Francis.Ielsch@e...>
To:
Date: Wed May 4 11:01:03 CEST 2005
Subject: [oc] Wishbone in UART16550
> Hello,
> I'm using the UART16550 core and there is something related to the
> implementation of wishbone that I disagree with.
> Under uart_top.v are 2 modules: uart_regs.v and uart_wb.v. Wishbone
> control signals are only provided to uart_wb.v and uart_regs.v
> receive
> address and data buses. I'm upsetted with the fact that uart_regs.v
> doesn't receive the strobe signal. Thus this module drives the
> output
> data bus even if the master isn't talking to it (strobe not
> asserted for
> this slave).
> I know that the wb_dat_i input of the master is a muxtiplexing of
> the
> wb_dat_o of all slave so it doesn't disturb when a slave drives its
> wb_dat_o whereas the master is talking to an other slave. However,
> I
> think it would be better that wishbone's slaves doesn't have any
> activity as long as they are not addressed.
> As I'm a new Wishbone user, I may be wrong. What are Wishbone
> Wizards
> thinking about my opinion ?
> Regards,
> Fran6
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