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Message
From: Mark McDougall<markm@v...>
Date: Fri Dec 2 03:49:20 CET 2005
Subject: [oc] IDE interface
slewis@b... wrote:> I want to find out this
> feasibility and possibly this idea and a timing diagram of a typical
> hard drive access sequence.
This information is available in the ATA specification.
Would I need to daisy chain the
> interface through the FPGA? Or could they simply be parrallel?
> Parrallel would require open drain outputs on signals like the chip
> selects, interrupt requests, etc in order to keep the two host
> interfaces (one in my FPGA and the second out on the motherboard)
> from stepping on each other. However, I haven't been able to locate
> this information. Has anyone done this before?
I can't comment on the electrical aspects of this, but I can assure you
from a system standpoint, you're asking for trouble. This is a sure way
to corrupt data on your harddisk, that's for sure!
I must admit I can't even think of why you'd want/need to do this??? If
you need to grant access to the PC harddisk data to a peripheral via an
FPGA, I would've thought you'd implement a communications channel over
PCI and have a driver request data via the OS?!?
If you are really hell-bent on doing it this way, then I'd suggest you
connect the drive solely via the FPGA and have your PC access the data
that way. Your system problems in regards to sharing a drive still
remain, but your electrical ones go away.
Regards,
--
Mark McDougall, Software Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
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