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Message
From: slewis at bdatech.com<slewis@b...>
Date: Thu Dec 1 22:00:03 CET 2005
Subject: [oc] IDE interface
I'm working on a PC board design that will have a Xilinx FX12 FPGA on
its mainboard. I want to run the IDE over to my FPGA so that my FPGA
has access to the hard drive. Generally a PC consists of a IDE
"Controller" ATA style which is located on any generic IDE hard drive
and an IDE "Host Interface" which is what you'll find on the mother
board's south bridge or Super I/O chip. What I want to do is
essentially add a second "IDE Host Interface" into my FPGA allowing it
access to the same hard drive as the rest of the PC uses. Since I
haven't designed IDE host interfaces before, I want to find out this
feasibility and possibly this idea and a timing diagram of a typical
hard drive access sequence. Would I need to daisy chain the interface
through the FPGA? Or could they simply be parrallel? Parrallel would
require open drain outputs on signals like the chip selects, interrupt
requests, etc in order to keep the two host interfaces (one in my FPGA
and the second out on the motherboard) from stepping on each other.
However, I haven't been able to locate this information. Has anyone
done this before?
Pappy
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