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    Navigation: All forums > Cores > Message List > Message Post

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    From: Arlen Cox<arlencox@g...>
    Date: Mon Nov 14 18:32:12 CET 2005
    Subject: [oc] design fpga board
    Top
    I won't blame you for not knowing JTAG. Even though it's standard
    there's remarkably little documentation on what exactly JTAG is
    online. In the FPGA sense, you can read about it in the datasheets
    provided by Xilinx, Altera, Lattice, Actel, etc. I recommend reading
    the datasheets. They have all of the info you absolutely need. App
    notes can also be helpful. Read those.

    If you haven't done research yourself most folks will not help you.

    -Arlen
    On 11/6/05, b.vijaykeshav@g... <b.vijaykeshav@g...> wrote:
    > sir,
    > i am b.vijay keshav an application engg in a stpl,hyderabad. i would like
    > to design the fpga board. i am Master in Technology graduate.my
    > speciallisation is vlsi design . i had a good concept in vhdl based
    > design. please help in doing the design
    > i dont have any idea on how this jtag works and how the fpga has to be
    > configured.
    > thanking you sir ,
    > with regrads ,
    > vijay keshav
    > _______________________________________________
    > http://www.opencores.org/mailman/listinfo/cores
    >

     
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