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Message
From: powerarm2001 at yahoo.co.in<powerarm2001@y...>
Date: Fri Sep 16 19:48:29 CEST 2005
Subject: [oc] Bus delay - FPGA
In FPGA design ,I have a 16 bit counter and I latch the counter value onto a data bus
and I read the data bus continuously. I make a very fast read out of
the data bus. I have problem here. There is delay in the data bus to
change from one counter value to another counter value. For example
let the counter value be 1403H.I latch it to the data bus. I read the
value. The next counter value will be 1404H. When I latch this data to
the data bus, each data line in the bus takes different time to arrive
at 1404h. For example data line 0 and 1 (0 and 1st Bit should be 0
here). But it takes much time to change state from 1 to 0.Before this
occurs bit 2 become 1.So I read the value 1407h. Can you suggest me
what to do with this transition delay.
Thanks.
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