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Message
From: xjf77 at opencores.org<xjf77@o...>
Date: Mon Sep 12 14:55:19 CEST 2005
Subject: [oc] DDR SDRAM controller read/write sequence
Dear all,
I am testing the DDR controller downloaded from opencores.org.
While in the readme file, the author did not mention when shall the user
give the memory address. Only read/write command and data sequence
are available.
I tried to give out the write command at first, then wait for the data-
request signal, as described in the readme. Two clocks after the
data_request, I give out the write data together with the destination
address. While onboard test failed! Though there is new data written
into the ddr, while not the data I want.
Could anyone tell me what is the correct read/write sequence?
thanks !
regards,
jianfeng
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