|
Message
From: xjf77 at yahoo.com<xjf77@y...>
Date: Fri Aug 26 15:12:38 CEST 2005
Subject: [oc] DDR SDRAM controller
Dear Cargnini,
I would like to discuss some problems with regards to MIG007. I
would like to generate the ddr sdram controller for for ML310 circuit
onboard 256MB DIMMs. I have the following problems.
1. MIG007 currently support only unbuffered DDR SDRAM. While my
onboard DIMMs is registered, dose this affects the operation?
2. In my case, I am wondering which memory type I can select
(component or dimms?). If select DIMMs, then SDRAM part data width is
restricted to 64/72 bits. While I see the EDK plb-ddr sdram for ML310
use only 32 bits of DDR SDRAM data pins. How dose it come? Feel
puzzled on it.
3. MIG007, as Anna said, seems to be not compatible with the real
circuit board pin out constraints, i.e., some real DQS pins are not
allowed to be allocated as DQS pin in MIG007-Pin Editor. It's better to
neglect the Pin Editor using my own ucf file, I think. Otherwise we have
to manually modify the generated ucf file to adapt to the board pin
connection.
That's it!
Thanks a lot in advace.
regards,
Jeff
----- Original Message -----
From: Luís Vitório Cargnini<cargnini@m...>
To:
Date: Thu Aug 11 06:15:45 CEST 2005
Subject: [oc] DDR SDRAM controller
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
> first upgrade your ise to 7.1.03i latest version, second yes i
> tested on
> board of memec with Spartan3-1500, i tested on board, and simulated
> too
> using a new tb made by me, instantiate generate a clock an put
> addr,
> data, we and see what you get.
> Well to do your interface and test if it working put the DDR
> controller
> write some addr on memory than read this address, or put a second
> hardware module that could read the memory outside fpga like a
> microcontroller and see what you get, a design kit will really help
> in
> this time, develop hw without a dev kit is a little .....too risk,
> is
> the better words. PLEASE verify your ucf, and verify the source
> code
> generated as i said i remember, mig generated defectuous code,
> check it
> signal by signal instantiation and interconnection by one, don't
> forget
> to check all of them first and depurate it.
> Anna D. Ashley wrote:
> | Good evening,
> |
> | thank you very much indeed for an answer.
> |
> | I think I should say some more words about my problem. I have an
> ucf
> | file which was provided with my board and in order to map all
> pins
> | correctly I used "Pin editor" of the mig007 tool.
> According to "How to
> ring
> | use" all red coloured pins are allowed to select for DQS
> from
> |
> |
> - --
> Thanks && Regards
> Luís Vitório Cargnini
> IEEE Member
> Mastering @ PUCRS - Electrical Engineer - Microelectronics
> Sponsored by CNPQ
> Computer Science Bachelor
> OpenCores Member <www.opencores.org>
> EuropeSwPatentFree <http://EuropeSwPatentFree.hispalinux.es>
> -----BEGIN PGP SIGNATURE-----
> Version: GnuPG v1.4.1 (FreeBSD)
>
iD8DBQFC+tDwII4c9KZOcnoRAmV0AJ4jBCDhWsQaFJT7nfM1vRxcehVE4QCg
r84m
> j89WR136v8IxvknnUPKBXtM=
> =XFbt
> -----END PGP SIGNATURE-----
>
>
|
 |
Browse
