OPENCORES.ORG

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Good evening,
thank you very much indeed for an answer.
I think I should say some more words about my problem. I have an ucf 
file which was provided with my board and in order to map all pins 
correctly I used "Pin editor" of the mig007 tool. According to "How to 
use" all red coloured pins are allowed to select for DQS from 
data/strobes list box but we he had to map some DQS to black coloured 
pins in order to follow ucf file which was provided with the board (I 
think I must follow it for having a working controller). The tool 
generated design successfully (after all pins were mapped) but I have 
lots of errors during translation (some of them I fixed). All errors are 
the same, e.g.

ERROR:NgdBuild:752 - Line 404 in '../par/mem_interface_top.ucf': Could 
not find instance(s) 'cntrl0_ddr1_dq(63)' in the design.  To suppress 
this error,  specify the correct instance name or remove the constraint. 
 The 'Allow Unmatched LOC Constraints' ISE property can also be set ( 
-aul switch for command line users ).
and here is the line

Line 404: INST "cntrl0_ddr1_dq(63)" LOC = AL32;

I have the same errors (NgdBuild:752) error for all data and strobe 
signals. This problem I can not fix. Sure I set all options in ISE GUI 
which were described on your web page.

I also have some questions related to your controller. Did you finally 
generated a working memory interface with the tool? For which board and 
FPGA did you do it? Did you test it with the real board or just simulate 
it? The last question is very important for me because I have to test my 
design with the board (without simulator) and I do not sure that I could 
use ddr_test_bench generated by the tool. Than I have to create my own 
interface in order to test the controller but currently I am not quite 
sure how to do it.

Thanks.

Best,
 Anna

Luís Vitório Cargnini wrote:

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> first thing i used mig, so i could help you, second is did what you
> want, Third you will have some problems 8-)
> The first thing to do with code generated by mig is check all the
> connections and pin type generated, i remember that mig generate one
> data-bus signals between buffers and a top interface have a path
> changed, must bu output and mig generate as input, check all of this
> first than your code will synthesize. Always when i had problem with mig
> in 2004 was this the problem, was one signal specifically, unfortunately
> i forgot what is the signal name 8-( .
>
> ada@c... wrote:
> | Hi all!
> | Curently I am a Master student and I am working on my master thesis.
> | And for some purposes I have to write or adapt a DDR SDRAM memory
> | controller (for Xilinx Virtex II board with xc2v4000 FPGA). First I
> | wanted to adapt DDR SDRAM memory controller from opencores projects
> | but there is no support and noone ansers questions:( Then I found the
> | Memory Interface Generator (mig007) tool from Xilinx and generated a
> | memory interfece. Unfortunatelly I have lots of errors during
> | translation (in ucf file after I defined all pins acording to my board
> | ucf file). I asked Xilinx but there is no answer. I do not know what
> | to do. Could someone help me? I would be glad to have any help.
> |
> | Best,
> |  Anna
> | _______________________________________________
> | http://www.opencores.org/mailman/listinfo/cores
> |