OPENCORES.ORG

Hi all!

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

first thing i used mig, so i could help you, second is did what you
want, Third you will have some problems 8-)
The first thing to do with code generated by mig is check all the
connections and pin type generated, i remember that mig generate one
data-bus signals between buffers and a top interface have a path
changed, must bu output and mig generate as input, check all of this
first than your code will synthesize. Always when i had problem with mig
in 2004 was this the problem, was one signal specifically, unfortunately
i forgot what is the signal name 8-( .

ada@c... wrote:
| Hi all!
| Curently I am a Master student and I am working on my master thesis.
| And for some purposes I have to write or adapt a DDR SDRAM memory
| controller (for Xilinx Virtex II board with xc2v4000 FPGA). First I
| wanted to adapt DDR SDRAM memory controller from opencores projects
| but there is no support and noone ansers questions:( Then I found the
| Memory Interface Generator (mig007) tool from Xilinx and generated a
| memory interfece. Unfortunatelly I have lots of errors during
| translation (in ucf file after I defined all pins acording to my board
| ucf file). I asked Xilinx but there is no answer. I do not know what
| to do. Could someone help me? I would be glad to have any help.
|
| Best,
|  Anna
| _______________________________________________
| http://www.opencores.org/mailman/listinfo/cores
|

- --
Thanks && Regards
Luís Vitório Cargnini
IEEE Member
Mastering @ PUCRS - Eletrical Engineer - Microeletronics
Sponsored by CNPQ
Computer Science Bachelor
OpenCores Member <www.opencores.org>
EuropeSwPatentFree <http://EuropeSwPatentFree.hispalinux.es>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.1 (FreeBSD)

iD8DBQFC+fKvII4c9KZOcnoRAt/WAJ0Y6QNJpW7HYpu3pQAjn6WvWjGYZgCdGkK2
A4toTZG9A2pNPrHjpTBF4MI=
=zEB3
-----END PGP SIGNATURE-----