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Message
From: InvalidError at gmail.com<InvalidError@g...>
Date: Thu Jul 28 21:03:11 CEST 2005
Subject: [oc] Project Beginnings
Most FPGA companies offer free tools for their FPGAs.ISE Webpack is not really limited in terms of gate count but it does
lack support for most Virtex FPGAs (no support for CoreGen so no MGT,
no PPC, no Ethernet MACs, etc.) and the largest Spartan 2/3 family
members. Although Webpack does not have an explicit gate count limit,
there is an implicit one in the form of the largest supported device
which is the XC3S1500 at the moment.
Some (at least Xilinx and Altera) also have special arrangements with
Mentor to provide free Modelsim. From the WebPack FAQ, it seems XE-III
does not have a complexity limit but simulation performance is
increasingly artificially degraded as the code exceeds 10k total
statements. Post-PAR simulation with timings for a nearly full 1.5M
gates FPGA would very likely be an exercise in patience. (RTL
simulations for a ~85% full XC2VP40 with Modelsim SE are already
fairly slow, PAR+timings on XE of the same would probably take forever.)
It is nice to have free stuff, all I need now is low-cost FPGAs (and
related tools) featuring Multi-Gigabit Transceivers. With everything
is going serial, interfacing PCs and PC-style components is becoming a
major chore: external PHYs cost $10 + ~40 pins each, are somewhat
elusive and supersizing the package to accomodate the external PHYs
probably adds more cost than integrating quad MGTs.
----- Original Message -----
From: MEDS INTERNATIONAL Quintin Immelman<quintin@m...>
To:
Date: Thu Jul 28 11:21:42 CEST 2005
Subject: [oc] Project Beginnings
> I'm using Xilinx Webpack 7.1i
> They have a free version avaliable from their website
> www.xilinx.com and don't forget to donwload Chipscope aswell they
> too have a free non-comercial version. The Webpack is only limited
> in code size upto 200000 gates I think and certain of the Virtex 4
> chips will not compile. Otherwise to get statred it's great!
> Hope this helps.
> Quintin Immelman
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