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Message
From: Guy Hutchison<ghutchis@g...>
Date: Mon Jul 25 20:56:05 CEST 2005
Subject: [oc] Project Beginnings
On 7/25/05, kevin <klynch@g...> wrote:
> I am interested in starting a project on here to create a standard 5
> stage pipeline MIPS core from the ground up. I know it's probably been
> beaten to death, but it's what I know.
Some start-of-project questions:
* What would this accomplish which has not been done by the existing
MIPS cores? If it's to write it in VHDL instead of Verilog, what
about porting an existing core to VHDL?
* What is your plan for dealing with MIPS legal issues?
> Before I start this, however, I have a few questions. I know VHDL but
> it seems as though most projects on here are Verilog.
I will skip my gut reaction to why not to code in VHDL. There are a
substantial number of VHDL cores on the site; if there are more
Verilog cores recently, it may be because there are more free
simulators available for Verilog now.
Other recommendations: MIPS related: If you don't have a copy of
Hennesey and Patterson, get one. On general core design, don't use
technology-specific components, and take RAMs and other components
which you know will have to be hardened and create generic models for
them.
- Guy
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