|
Message
From: kevin<klynch@g...>
Date: Mon Jul 25 20:28:37 CEST 2005
Subject: [oc] Project Beginnings
Hello all,I would just like to start out by commending you and this site for a
job well done.
I am interested in starting a project on here to create a standard 5
stage pipeline MIPS core from the ground up. I know it's probably been
beaten to death, but it's what I know.
Before I start this, however, I have a few questions. I know VHDL but
it seems as though most projects on here are Verilog. Is there a
reason for this? I have been writing my VHDL in Symphony EDA (Free
version) but it is a crippled, reduced speed version. I was wondering
if there was anything better that you can recommend. I would like to
work in Linux, but if I must I can work in Windows.
Are there any recommended environments out there? I have found FreeHDL
[1], but it seems incomplete from what I gather.
Also, does anyone have any guides/comments/tips for me before I start,
either MIPS related or general core design?
I plan on this being a work in progress for a while and I will
probably only submit a project when this becomes somewhat substantial.
Thanks,
Kevin Lynch
[1] http://www.freehdl.seul.org/index.html
|
 |
Browse
