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From: kinwong67 at hotmail.com<kinwong67@h...>
Date: Mon Jun 20 19:05:24 CEST 2005
Subject: [oc] I2C slave model
Hi,

I am looking for I2C slave with Verilog. Where can I find the I2C slave
Verilog code that Vika mentioned?

Thanks,
Kin

----- Original Message -----
From: vikasakalwadi@r...
To: sacmani@h..., cores@o...
Date: Wed, 13 Mar 2002 12:39:40 +0100
Subject: Re: [oc] I2C slave model

>
>
> hi,
> i had developed a simple i2c bus master in VHDL and was using I2C
> slave verilog code taht was available over here for the purpose of
> testing. When i am giving the start, and the address of the slave,
> the
> slave is not generating the acknowledgement bit. Since i donot know
> verilog, i couldnot figureout why such problem came up.
> Shouldn't the slave send an acknowledgement bit after the master
> addresses it ? If yes, can anybody let me know it the verilog slave
> code available over here would respond with the acknowledement bit
> or
> not ?
> Also let me know if there is slave module for simualtion in VHDL
> anywhere on the web.
> Thanking you all in advance
> regards,
> Vikas
>