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From: gaobo007008 at yahoo.com.cn<gaobo007008@y...>
Date: Fri Jun 10 17:22:35 CEST 2005
Subject: [oc] urgent enquire about the I2C master core!
When I use the tst_bench_top.v, I can't get the expected waveform
and in the console window it displays some error as follows,

run 20000ns
# :
# : status: 0 Testbench started
# :
# :
# :
# : INFO: WISHBONE MASTER MODEL INSTANTIATED (tst_bench_top.u0)
# :
# : status: 500 done reset
# : status: 5600 programmed registers
# : status: 9600 verified registers
# : status: 12600 core enabled
# : status: 17600 generate 'start', write cmd 20 (slave
address+write)
# : status: 20600 tip==0
# : status: 25600 write slave memory address 01
# : status: 28600 tip==0
# : status: 33600 write data a5
# : status: 36600 tip==0
# : status: 41600 write next data 5a, generate 'stop'
# : status: 44600 tip==0
# : status: 49600 generate 'repeated start', write cmd 21
(slave address+read)
# : status: 52600 tip==0
# : status: 55600 read + ack
# : status: 58600 tip==0
# :
# : ERROR: Expected a5, received 21 at time 61600
# : status: 64600 read + ack
# : status: 67600 tip==0
# :
# : ERROR: Expected 5a, received 21 at time 70600
# : status: 73600 read + ack
# : status: 76600 tip==0
# : status: 79600 received 21 from 3rd read address
# : status: 82600 read + nack
# : status: 85600 tip==0
# : status: 88600 received 21 from 4th read address
# :
# :
# : status: 338600 Testbench done
# RUNTIME: RUNTIME_0068 tst_bench_top.v (376): $finish called.
# KERNEL: Time: 3386 ns, Iteration: 0, Instance: \.
# KERNEL: stopped at time: 3386 ns

I don't know why this happens and why the slave memory always
received the 21. I have tried my best to settle this problems but I can't
conquer them.

BTW, the synthesis tool I use is Active HDL 6.1.

Thanks in advance.