OPENCORES.ORG

	Hi all,
	it's easy, just take a "adder" and build this simple circuit:
	R(n+1) = R(n) + C
	R ... Result
	n ... time tick
	C ... Constant

	The frequency out is the "normal"  CARRY OUT" of the adder.
	The f-out is a direct function of "C". Frequency range and
resolution can be influenced
	by selecting the bit-width of the adder and of course the input
clock frequency..
	And if you want a duty cycle of 50%, but a "divide by 2 - Flip Flop"
behind it.
	-- Simple but the best ;-)))  --

	Important: Adder and divider have to be synchronous and clocked.

	Hope this helps Frank

	_______________________________________________________________
	

	What exactly are you looking for? What divisors do you need to be
able
	to use? Integer only? Do you need to be able to maintain a 50 50
duty
	cycle?

	If you want a generic solution, you can easily implement a phase
	accumulator, which is normally found in a DDFS (Direct Digital
	Frequency Synthesis) unit. It will allow you to synthesize any
	frequency you would like (that is 1/2 of your driver clock frequency
	or less) as long as you don't require a strict 50 50 duty cycle.

	On 6/6/05, vmb1980@y... <vmb1980@y...> wrote:
	> Dear friend,
	>           I searched the google for vhdl coding for frequency
divider. I
	> saw your request here. could you please send me that if you got
the
	> code.
	>    I understand that you send this request on 2002 apr, still iam
asking
	> you.
	> Thanks,
	> mukundan
	> 
	> ----- Original Message -----
	> From: lamps98@h...
	> To: cores@o...
	> Date: Wed, 17 Apr 2002 05:21:36 +0200
	> Subject: [oc] VHDL code - FREQUENCY DIVIDER
	> 
	> >
	> >
	> > i desperately need  the VHDL code for a frequency divider
....the
	> > frequency divider circuit uses a 4 X 4 adder and a D-latch with
	> > reset
	> > and a MUX
	> >
	> _______________________________________________
	> http://www.opencores.org/mailman/listinfo/cores
	>
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