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Message
From: avi_iitd2002 at yahoo.co.in<avi_iitd2002@y...>
Date: Fri Jun 3 09:28:57 CEST 2005
Subject: [oc] Re: [video] VGA controller implementation
yaar can anyone give me the xilinx_ram_dp in verilog...
thnx
avinash
----- Original Message -----
From: Shawn Tan <shawn.tan@a...>
To: Nash Haramaini <nash_h02@y...>
cores@o...
Date: 15 Nov 2002 11:33:11 +0800
Subject: [oc] Re: [video] VGA controller implementation
>
>
> On Fri, 2002-11-15 at 10:45, Nash Haramaini wrote:
> >
> > Thanks for your information, can i get your verilog file, I
> really need it
> > especially your bloks rams.
> >
>
> Hope this helps... and I've posted one copy to Opencores.org.. in
> case
> anyone else asks for it in the future... It's in VHDL
> unfortunately.. I
> was doing VHDL at the time... but you should be able to translate
> it to
> verilog easily... the RAM translations were due to the fact that
> FC2
> didn't detect them automatically...
>
> --
> with metta,
> Shawn Tan.
>
> -------------------------------------------------------------------
----
> Mobile : +60 (12) 376-1667 ICQ UIN :
> 1802628
> "The future will be governed by Stupidity, Selfishness and
> Horniness"
>
>
>
> -------------------------------------------------------------------
------------
> -- Title : Xilinx RAMS
> -- Project : Simple Xilinx implementation
>
> -------------------------------------------------------------------
------------
> -- File : xram.vhd
> -- Author : Shawn Tan
> -- Created : 2002/04/16
> -- Last modified :
>
> -------------------------------------------------------------------
------------
> -- Description : Maps RAMB* to XRAMB*
>
> -------------------------------------------------------------------
------------
>
> -- RAMB4_s16
> library simprim;
> use simprim.vpackage.all;
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_arith.all;
> use ieee.std_logic_unsigned.all;
>
> entity ramb4_s16 is
>
> port (DI : in STD_LOGIC_VECTOR (15 downto 0);
> EN : in STD_ULOGIC;
> WE : in STD_ULOGIC;
> RST : in STD_ULOGIC;
> GSR : in STD_ULOGIC;
> CLK : in STD_ULOGIC;
> ADDR : in STD_LOGIC_VECTOR (7 downto 0);
> DO : out STD_LOGIC_VECTOR (15 downto 0)
> );
>
> end entity;
>
> architecture ramrtl of ramb4_s16 is
>
> component x_ramb4_s16 is
> port (DI : in STD_LOGIC_VECTOR (15 downto 0);
> EN : in STD_ULOGIC;
> WE : in STD_ULOGIC;
> RST : in STD_ULOGIC;
> GSR : in STD_ULOGIC;
> CLK : in STD_ULOGIC;
> ADDR : in STD_LOGIC_VECTOR (7 downto 0);
> DO : out STD_LOGIC_VECTOR (15 downto 0)
> );
> end component;
>
> begin
> ramb4s16: x_ramb4_s16 port map ( DI, EN, WE, RST, GSR,
CLK, ADDR,
> DO );
> end architecture;
>
>
> -- RAMB4_s4
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_arith.all;
> use ieee.std_logic_unsigned.all;
>
> entity ramb4_s4 is
> port (DI : in STD_LOGIC_VECTOR (3 downto 0);
> EN : in STD_ULOGIC;
> WE : in STD_ULOGIC;
> RST : in STD_ULOGIC;
> GSR : in STD_ULOGIC;
> CLK : in STD_ULOGIC;
> ADDR : in STD_LOGIC_VECTOR (9 downto 0);
> DO : out STD_LOGIC_VECTOR (3 downto 0)
> );
> end entity;
>
> architecture ramrtl of ramb4_s4 is
>
> component x_ramb4_s4 is
> port (DI : in STD_LOGIC_VECTOR (3 downto 0);
> EN : in STD_ULOGIC;
> WE : in STD_ULOGIC;
> RST : in STD_ULOGIC;
> GSR : in STD_ULOGIC;
> CLK : in STD_ULOGIC;
> ADDR : in STD_LOGIC_VECTOR (9 downto 0);
> DO : out STD_LOGIC_VECTOR (3 downto 0)
> );
> end component;
>
> begin
> ramb4s4: x_ramb4_s4 port map ( DI, EN, WE, RST, GSR, CLK,
ADDR, DO
> );
> end architecture;
>
>
> -- RAMB4_s8
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_arith.all;
> use ieee.std_logic_unsigned.all;
>
> entity ramb4_s8 is
> port (DI : in STD_LOGIC_VECTOR (7 downto 0);
> EN : in STD_ULOGIC;
> WE : in STD_ULOGIC;
> RST : in STD_ULOGIC;
> GSR : in STD_ULOGIC;
> CLK : in STD_ULOGIC;
> ADDR : in STD_LOGIC_VECTOR (8 downto 0);
> DO : out STD_LOGIC_VECTOR (7 downto 0)
> );
> end entity;
>
> architecture ramrtl of ramb4_s8 is
>
> component x_ramb4_s8 is
> port (DI : in STD_LOGIC_VECTOR (7 downto 0);
> EN : in STD_ULOGIC;
> WE : in STD_ULOGIC;
> RST : in STD_ULOGIC;
> GSR : in STD_ULOGIC;
> CLK : in STD_ULOGIC;
> ADDR : in STD_LOGIC_VECTOR (8 downto 0);
> DO : out STD_LOGIC_VECTOR (7 downto 0)
> );
> end component;
>
> begin
> ramb4s8: x_ramb4_s8 port map ( DI, EN, WE, RST, GSR, CLK,
ADDR, DO
> );
> end architecture;
>
>
>
> -- RAMB4_s16_s16
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_arith.all;
> use ieee.std_logic_unsigned.all;
>
> entity ramb4_s16_s16 is
> port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
> DIB : in STD_LOGIC_VECTOR (15 downto 0);
> ENA : in STD_ULOGIC;
> ENB : in STD_ULOGIC;
> WEA : in STD_ULOGIC;
> WEB : in STD_ULOGIC;
> RSTA : in STD_ULOGIC;
> RSTB : in STD_ULOGIC;
> GSR : in STD_ULOGIC;
> CLKA : in STD_ULOGIC;
> CLKB : in STD_ULOGIC;
> ADDRA : in STD_LOGIC_VECTOR (7 downto 0);
> ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
> DOA : out STD_LOGIC_VECTOR (15 downto 0);
> DOB : out STD_LOGIC_VECTOR (15 downto 0)
> );
> end entity;
>
> architecture ramrtl of ramb4_s16_s16 is
>
> component x_ramb4_s16_s16 is
>
> port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
> DIB : in STD_LOGIC_VECTOR (15 downto 0);
> ENA : in STD_ULOGIC;
> ENB : in STD_ULOGIC;
> WEA : in STD_ULOGIC;
> WEB : in STD_ULOGIC;
> RSTA : in STD_ULOGIC;
> RSTB : in STD_ULOGIC;
> GSR : in STD_ULOGIC;
> CLKA : in STD_ULOGIC;
> CLKB : in STD_ULOGIC;
> ADDRA : in STD_LOGIC_VECTOR (7 downto 0);
> ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
> DOA : out STD_LOGIC_VECTOR (15 downto 0);
> DOB : out STD_LOGIC_VECTOR (15 downto 0)
> );
> end component;
>
> begin
> ramb4s16s16: x_ramb4_s16_s16 port map ( DIA, DIB, ENA,
ENB, WEA,
> WEB, RSTA, RSTB, GSR, CLKA, CLKB, ADDRA, ADDRB, DOA, DOB);
> end architecture;
>
> -- RAMB4_s8_s8
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_arith.all;
> use ieee.std_logic_unsigned.all;
>
> entity ramb4_s8_s8 is
> port (DIA : in STD_LOGIC_VECTOR (7 downto 0);
> DIB : in STD_LOGIC_VECTOR (7 downto 0);
> ENA : in STD_ULOGIC;
> ENB : in STD_ULOGIC;
> WEA : in STD_ULOGIC;
> WEB : in STD_ULOGIC;
> RSTA : in STD_ULOGIC;
> RSTB : in STD_ULOGIC;
> GSR : in STD_ULOGIC;
> CLKA : in STD_ULOGIC;
> CLKB : in STD_ULOGIC;
> ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
> ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
> DOA : out STD_LOGIC_VECTOR (7 downto 0);
> DOB : out STD_LOGIC_VECTOR (7 downto 0)
> );
> end entity;
>
> architecture ramrtl of ramb4_s8_s8 is
>
> component x_ramb4_s8_s8 is
> port (DIA : in STD_LOGIC_VECTOR (7 downto 0);
> DIB : in STD_LOGIC_VECTOR (7 downto 0);
> ENA : in STD_ULOGIC;
> ENB : in STD_ULOGIC;
> WEA : in STD_ULOGIC;
> WEB : in STD_ULOGIC;
> RSTA : in STD_ULOGIC;
> RSTB : in STD_ULOGIC;
> GSR : in STD_ULOGIC;
> CLKA : in STD_ULOGIC;
> CLKB : in STD_ULOGIC;
> ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
> ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
> DOA : out STD_LOGIC_VECTOR (7 downto 0);
> DOB : out STD_LOGIC_VECTOR (7 downto 0)
> );
> end component;
>
> begin
> ramb4s8s8: x_ramb4_s8_s8 port map ( DIA, DIB, ENA, ENB,
WEA, WEB,
> RSTA, RSTB, GSR, CLKA, CLKB, ADDRA, ADDRB, DOA, DOB);
> end architecture;
>
>
>
>
>
>
> -------------------------------------------------------------------
------------
> -- Title : Xilinx RAMS
> -- Project : Simple Xilinx implementation
>
> -------------------------------------------------------------------
------------
> -- File : xram.vhd
> -- Author : Shawn Tan
> -- Created : 2002/04/16
> -- Last modified :
>
> -------------------------------------------------------------------
------------
> -- Description : Maps RAMB* to XRAMB*
>
> -------------------------------------------------------------------
------------
>
> -- RAMB4_s16
> --library simprim;
> --use simprim.vpackage.all;
>
> -- CMEMSPRAM
> --library simprim;
> --use simprim.vpackage.all;
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_arith.all;
> use ieee.std_logic_unsigned.all;
>
> entity xilinx_ram_sp is
>
> port (DI : in STD_LOGIC_VECTOR (23 downto 0);
> EN : in STD_ULOGIC;
> WE : in STD_ULOGIC;
> RST : in STD_ULOGIC;
> --GSR : in STD_ULOGIC;
> CLK : in STD_ULOGIC;
> ADDR : in STD_LOGIC_VECTOR (8 downto 0);
> DO : out STD_LOGIC_VECTOR (23 downto 0)
> );
>
> end entity;
>
> architecture ramrtl of xilinx_ram_sp is
>
> component ramb4_s8 is
> port (DI : in STD_LOGIC_VECTOR (7 downto 0);
> EN : in STD_ULOGIC;
> WE : in STD_ULOGIC;
> RST : in STD_ULOGIC;
> --GSR : in STD_ULOGIC;
> CLK : in STD_ULOGIC;
> ADDR : in STD_LOGIC_VECTOR (8 downto 0);
> DO : out STD_LOGIC_VECTOR (7 downto 0)
> );
> end component;
>
> signal ri,ro,gi,go,bi,bo:std_logic_vector(7 downto 0);
>
> begin
> ri <= DI(23 downto 16);
> gi <= DI(15 downto 8);
> bi <= DI(7 downto 0);
>
> DO(23 downto 16) <= ro;
> DO(15 downto 8) <= go;
> DO(7 downto 0) <= bo;
>
> SPRAMR: RAMB4_S8 port map ( ri, EN, WE, RST, CLK, ADDR,
ro );
> SPRAMG: RAMB4_S8 port map ( gi, EN, WE, RST, CLK, ADDR,
go );
> SPRAMB: RAMB4_S8 port map ( bi, EN, WE, RST, CLK, ADDR,
bo );
> end architecture;
>
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_arith.all;
> use ieee.std_logic_unsigned.all;
>
> entity xilinx_ram_dp is
> port (DIA : in STD_LOGIC_VECTOR (23 downto 0);
> DIB : in STD_LOGIC_VECTOR (23 downto 0);
> ENA : in STD_ULOGIC;
> ENB : in STD_ULOGIC;
> WEA : in STD_ULOGIC;
> WEB : in STD_ULOGIC;
> RSTA : in STD_ULOGIC;
> RSTB : in STD_ULOGIC;
> --GSR : in STD_ULOGIC;
> CLKA : in STD_ULOGIC;
> CLKB : in STD_ULOGIC;
> ADDRA : in STD_LOGIC_VECTOR (6 downto 0);
> ADDRB : in STD_LOGIC_VECTOR (6 downto 0);
> DOA : out STD_LOGIC_VECTOR (23 downto 0);
> DOB : out STD_LOGIC_VECTOR (23 downto 0)
> );
> end entity;
>
> architecture ramrtl of xilinx_ram_dp is
>
> component ramb4_s8_s8 is
> port (DIA : in STD_LOGIC_VECTOR (7 downto 0);
> DIB : in STD_LOGIC_VECTOR (7 downto 0);
> ENA : in STD_ULOGIC;
> ENB : in STD_ULOGIC;
> WEA : in STD_ULOGIC;
> WEB : in STD_ULOGIC;
> RSTA : in STD_ULOGIC;
> RSTB : in STD_ULOGIC;
> --GSR : in STD_ULOGIC;
> CLKA : in STD_ULOGIC;
> CLKB : in STD_ULOGIC;
> ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
> ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
> DOA : out STD_LOGIC_VECTOR (7 downto 0);
> DOB : out STD_LOGIC_VECTOR (7 downto 0)
> );
> end component;
>
> signal ria,rib,gia,gib,bia,bib,roa,rob,goa,gob,boa,bob:
> std_logic_vector(7 downto 0);
> signal adr_a,adr_b:std_logic_vector(8 downto 0);
> begin
> adr_a(6 downto 0) <= ADDRA; adr_a(8 downto 7) <= "00";
> adr_b(6 downto 0) <= ADDRB; adr_b(8 downto 7) <= "00";
>
> ria <= DIA(23 downto 16); rib <= DIB(23 downto 16);
> gia <= DIA(15 downto 8); gib <= DIB(15 downto 8);
> bia <= DIA(7 downto 0); bib <= DIB(7 downto 0);
>
> DOA(23 downto 16) <= roa; DOB(23 downto 16) <= rob;
> DOA(15 downto 8) <= goa; DOB(15 downto 8) <= gob;
> DOA(7 downto 0) <= boa; DOB(7 downto 0) <= bob;
>
> DPRAMR: RAMB4_S8_S8 port
> map(ria,rib,ENA,ENB,WEA,WEB,RSTA,RSTB,CLKA,CLKB,adr_a,adr_b,
> roa,rob);
> DPRAMG: RAMB4_S8_S8 port
> map(gia,gib,ENA,ENB,WEA,WEB,RSTA,RSTB,CLKA,CLKB,adr_a,adr_b,
> goa,gob);
> DPRAMB: RAMB4_S8_S8 port
> map(bia,bib,ENA,ENB,WEA,WEB,RSTA,RSTB,CLKA,CLKB,adr_a,adr_b,
> boa,bob);
> end architecture;
>
>
> <P>pgp00000.pgp</P>
>
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