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Message
From: zhangchao27 at yahoo.com.cn<zhangchao27@y...>
Date: Thu Jun 2 10:03:17 CEST 2005
Subject: [oc] rc4 in verilog
I am an student,and a chinese too. I just study the verilog not a long
time . now ,I have a problem . I don`t know how to describe the 256*8
memory in verilog . someone told me a way : 8bits address ,64columns,
32rows, and 7-3bits connect a 1-32bit decoder, to chose the
row .address bits 2-0 to chose the bit. each 8 columns refer bit7 ,bit6,
bit5 ,bit4 ,bit3,bit2 ,bit1 ,bit0 .
if you know someone`s work about rc4 , you can email to me, tell me
about his work.
please forgive me my poor english
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