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Message
From: Redant Steven<redant@i...>
Date: Thu Apr 28 15:27:10 CEST 2005
Subject: [oc] Searching for a 16550 uart in VHDL
What's your problem with translating it?
Translating synthesizeable Verilog in VHDL should be easy...
> -----Original Message-----
> From: john@l... [mailto:john@l...]
> Sent: Wednesday, April 27, 2005 16:13
> To: cores@o...
> Subject: [oc] Searching for a 16550 uart in VHDL
>
>
> Hello,
>
> Does anyone have a VHDL-translation from the verilog 16550 uart so
> nicely done in the projects.
>
> I cant get it translated from verilog to VHDL
>
> Doesn't have to be Wishbone compatible.
> It could also be a different one, or Xilinx specific (I use a
> Spartan 3)
> (internal dual port rams).
>
> Thanks in advance
>
> John van Zijl
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
>
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