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Message
From: Roberto Ammendola<roberto.ammendola@r...>
Date: Wed Apr 20 14:56:08 CEST 2005
Subject: [oc] Operations within a vector
A VHDL how-would-you-do-this question (if allowed here).Suppose you have a parametric generation of instances of a certain
component.
Something like:
inst_generator: for i in 0 to PARAMETER generate
my_inst: component_name
port map(
a => a(i), -- an in signal, std_logic type
b => b(i) -- an out signal, std_logic type
);
end generate;
Now suppose that you want to OR (or whatever) a certain out signal of
the port map of a certain instance with the same signal from all the
instances; in our case a std_logic_vector(PARAMETER downto 0) global_b
which would be:
global_b <= b(0) or b(1) or ... or b(PARAMETER-1) or b(PARAMETER);
So, how would you calculate global_b, keeping the parametric feature in
your code?
And, more complex, what if b is a vector itself?
greetings
Roberto
--
______________________________________________________________________
Roberto Ammendola INFN - Roma II - APE group
tel: +39-0672594504 email: roberto.ammendola@r... // \
Via della Ricerca Scientifica 1 - 00133 Roma \\_/ //
__________________________________________ ''-.._.-''-.._.. -(||)(')
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