LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Sponsors
  • Mirrors
  • Logos
  • Contact us
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cores > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: Jai Dhar<jdhar@e...>
    Date: Tue Apr 12 18:49:51 CEST 2005
    Subject: [oc] Sony IRCS Core
    Top
    Thanks for your tips Mark, I have replied below.

    Quoting Mark McDougall <markm@v...>:

    > Jai Dhar wrote:
    >
    > > These two
    > > codes (7 bit and 8 bit) are currently parallel outputs.
    >
    > 15 bits of parallel output could be inconvenient to low-end micros (with
    > 8-bit data bus). You'd have to decode 2 separate addresses or use two
    > GPIO ports (micro-controller).
    >
    > You may wish to consider an 8-bit wide FIFO to store a couple of
    > device/command pairs (serially) whilst the host is too busy to process
    > and/or has a high interrupt latency. This could be useful if interfacing
    > to a small micro that disables interrupts for a while when it's doing
    > something else.
    >

    So providing CLK+Data may be better I take it?

    > > - when valid data is received, raise an interrupt pin. - Data bus
    > > (both cmd and dev. registers) are constantly updated - When user
    > > wishes to strobe data, assert an ack signal that clears the
    > > interrupt.
    >
    > Are you contemplating an edge or level interrupt signal? I suspect level
    > is easier to implement (eg. tie to FIFO not empty). Don't know whether
    > you want to bother considering (host) interrupt sharing issues?!?
    >
    > Without a FIFO simply reading the register (RD strobe) could clear the
    > interrupt. With a FIFO you could use the FIFO empty to control the
    > interrupt line. I'd also consider having an interrupt enable/disable as
    > well.
    >

    Level sensitive interrupt, mostly for the reasons you mentioned. Point noted
    about the int. en/dis.

    > > Essentially, it is up to the user to respond as fast as they wish -
    > > the data will constantly be updated even if the interrupt isn't
    > > serviced.
    >
    > Depends on whether or not a missed command is important. Using a FIFO
    > could cause a lot less headaches for low-end host processors...
    >

    i'm thinking with remote controls, the last button press is most important. This
    will be highly individual however. Thanks for the hints!

    > Regards,
    >
    > --
    > Mark McDougall, Software Engineer
    > Virtual Logic Pty Ltd, <http://www.vl.com.au>
    > 21-25 King St, Rockdale, 2216
    > Ph: +612-9599-3255 Fax: +612-9599-3266
    >




    ----------------------------------------
    This mail sent through www.mywaterloo.ca

    ----- End forwarded message -----




    ----------------------------------------
    This mail sent through www.mywaterloo.ca

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.